ENGINSOURECE

2010-03-05T09:11:00.001-08:00

VHDL CODE

2009-04-19T10:50:00.001-07:00

The belpw code is according to the vtu syllabus 4 sem ec and tc
1. 2:4 decoder
VHDL
entity decoder_2_4 is
port(D: in std_logic_vector(1 downto 0);
E: in std_logic;
Dout: out std_logic_vector(3 downto 0));
end decoder_2_4;
architecture Behavioral of decoder_2_4 is
begin
process(D,E)
begin
if (E = '0') then
Dout <= "0000";
else
case D is
when "00" => Dout <= "0001";
when "01" => Dout <= "0010";
when "10" => Dout <= "0100";
when others => Dout <= "1000";
end case;
end if;
end process;
end Behavioral;

2. 8:3 encoder without priority
entity encoder_8_3 is
port(D: in std_logic_vector(7 downto 0);
E: in std_logic;
Dout: out std_logic_vector(2 downto 0));
end encoder_8_3;
architecture Behavioral of encoder_8_3 is
begin
process(D,E)
begin
if (E = '0') then
Dout <= "ZZZ";
else
case D is
when "00000001" => Dout <= "000";
when "00000010" => Dout <= "001";
when "00000100" => Dout <= "010";
when "00001000" => Dout <= "011";
when "00010000" => Dout <= "100";
when "00100000" => Dout <= "101";
when "01000000" => Dout <= "110";
when others => Dout <= "111";
end case;
end if;
end process;
end Behavioral;

3. 8:3 encoder with priority
entity encoder_priority_8_3 is
port(D: in std_logic_vector(7 downto 0);
E: in std_logic;
Dout: out std_logic_vector(2 downto 0));
end encoder_priority_8_3;
architecture Behavioral of encoder_priority_8_3 is
begin
process (D,E)
begin
if (E = '0') then
Dout <= "ZZZ";
else
if (D(7) = '1') then Dout <= "111";
elsif (D(6) = '1') then Dout <= "110";
elsif (D(5) = '1') then Dout <= "101";
elsif (D(4) = '1') then Dout <= "100";
elsif (D(3) = '1') then Dout <= "011";
elsif (D(2) = '1') then Dout <= "010";
elsif (D(1) = '1') then Dout <= "001";
elsif (D(0) = '1') then Dout <= "000";
end if;
end if;
end process;
end Behavioral;

4. 8:1 Multiplexer
entity multiplexer_8_1 is
port(I: in std_logic_vector(7 downto 0);
E: in std_logic;
S: in std_logic_vector(2 downto 0);
Y: out std_logic);
end multiplexer_8_1;

architecture Behavioral of multiplexer_8_1 is
begin
process(I,E,S)
begin
if (E = '0') then
Y <= 'Z';
else
case s is
when "000" => Y <= I(0);
when "001" => Y <= I(1);
when "010" => Y <= I(2);
when "011" => Y <= I(3);
when "100" => Y <= I(4);
when "101" => Y <= I(5);
when "110" => Y <= I(6);
when others => Y <= I(7);
end case;
end if;
end process;
end Behavioral;

5. 4 bit binary to grey converter
VHDL
entity B_to_G is
Port(B: in std_logic_vector(3 downto 0);
G: out std_logic_vector(3 downto 0));
end B_to_G;
architecture Behavioral of B_to_G is
begin
G(3) <= B(3);
G(2)<= B(2) xor B(3);
G(1)<= B(1) xor B(2);
G(0)<= B(0) xor B(1);
end Behavioral;

6. 1:4 demultiplexer
entity demultiplexer_1_4 is
port(D: in std_logic;
S: in std_logic_vector(1 downto 0);
Dout: out std_logic_vector(3 downto 0));
end demultiplexer_1_4;

architecture Behavioral of demultiplexer_1_4 is
begin
process(S,D)
begin
Dout <= "0000";
case s is
when "00" => Dout(0) <= D;
when "01" => Dout(1) <= D;
when "10" => Dout(2) <= D;
when others => Dout(3) <= D;
end case;
end process;
end Behavioral;

7. N bit comparator
entity N_bit_comparator is
generic (N: integer := 3);
port(a,b: in std_logic_vector(N downto 0);
AGB,ALB,AEB: out std_logic);
end N_bit_comparator;
architecture Behavioral of N_bit_comparator is
begin
process(a,b)
begin
if(aelse ALB <= '0';
end if;

if (a>b) then AGB <= '1';
else AGB <= '0';
end if;

if (a=b) then AEB<='1';
else AEB<='0';
end if;

end process;
end Behavioral;

8. Full adder Data flow model
entity full_adder_df is
port(a,b,c: in std_logic;
Sum, Cout: out std_logic);
end full_adder_df;
architecture Behavioral of full_adder_df is
begin
Sum <= a xor b xor c;
Cout <= (a and b) or (b and c) or (c and a);
end Behavioral;

9. Full adder behavioral model
entity full_adder_beh is
port(a,b,c: in std_logic;
Sum,Cout: out std_logic);
end full_adder_beh;
architecture Behavioral of full_adder_beh is
begin
process (a,b,c)
variable T1,T2,T3,S1:std_logic;
begin
T1:=a and b;
T2:=b and c;
T3:=c and a;
S1:=a xor b;
Sum <= S1 xor c;
Cout <= T1 or T2 or T3;
end process;
end Behavioral;

10. Full adder Structural model
entity full_adder_str is
port(a,b,c : in std_logic;
Sum, Cout : out std_logic);
end full_adder_str;
architecture structural of full_adder_str is
component half_adder
port(h1,h2:in std_logic;
h3,h4:out std_logic);
end component;
signal temp1,temp2,temp3:std_logic;
begin
HA1:half_adder port map (a,b,temp2,temp1);
HA2:half_adder port map (temp2,z,Sum,temp3);
Cout <= temp1 or temp3;
end structural;

11. Full adder mixed model
entity full_adder_mixed is
port(a,b,c: in std_logic;
Sum,Cout: out std_logic);
end full_adder_mixed;
architecture mixed of full_adder_mixed is
begin
component xor_2
port(x1,x2: in std_logic;
x3: out std_logic);
end component;
signal S1: std_logic;
begin
XO1: xor_2 portmap (a,b,S1);
Sum <= S1 xor c;
process(a,b,c)
variables T1,T2,T3: std_logic;
begin
T1 := a and b;
T2 := b and c;
T3 := c and a;
Cout <= T1 or T2 or T3;
end process;
end mixed;
end Behavioral;

12. 8 bit ALU
VHDL
entity ALU_8_bit is
port(a,b: in std_logic_vector(7 downto 0);
sel: in std_logic_vector(2 downto 0);
E : in std_logic;
output: out std_logic_vector(7 downto 0));
end ALU_8_bit;
architecture Behavioral of ALU_8_bit is
begin
process(a,b,E,sel)
begin
if (E = '1') then
output <= (others => 'Z');
else
case sel is
when "000" => output <= a+b;
when "001" => output <= a-b;
when "010" => output <= a and b;
when "011" => output <= a or b;
when "100" => output <= a xor b;
when "101" => output <= a xnor b;
when "110" => output <= a nand b;
when others => output <= a nor b;
end case;
end if;
end process;
end Behavioral;

13. D flip flop
VHDL
entity D_flip_flop is
port(D,clk,rst: in std_logic;
Q: inout std_logic;
Qb: out std_logic);
end D_flip_flop;
architecture Behavioral of D_flip_flop is
signal clk_div: std_logic_vector(25 downto 0);
signal int_clk: std_logic;
begin
process (clk)
begin
if (clk='1' and clk'event) then
clk_div <= clk_div+1;
end if;
end process;
int_clk <= clk_div(20);
process(int_clk)
begin
if (rst='1') then
Q <= '0';
elsif (int_clk = '1' and int_clk'event) then
Q <= D;
end if;
end process;
Qb <= not Q;
end Behavioral;

14. T flip flop
entity T_flip_flop is
port(T,clk: in std_logic;
Q: inout std_logic:='0';
Qb: inout std_logic:='1');
end T_flip_flop;
architecture Behavioral of T_flip_flop is
signal clk_div: std_logic_vector(25 downto 0):= (others=>'0');
signal int_clk: std_logic:='0';
begin
process(clk)
begin
if (clk='1' and clk'event) then
clk_div <= clk_div + 1;
end if;
end process;
int_clk <= clk_div(20);
process(int_clk)
begin
if (int_clk='1' and int_clk'event) then
if (T ='1') then Q <= not Q; Qb<=not Qb;
elsif (T='0') then Q<=Q; Qb<=Qb;
end if;
end if;
end process;
end Behavioral;

15. SR flip flop
entity sr_flip_flop is
port(s,r,clk,rst: in std_logic;
Q,Qb: inout std_logic);
end sr_flip_flop;
architecture Behavioral of sr_flip_flop is
signal clk_div:std_logic_vector(25 downto 0):=(others=>'0');
signal int_clk: std_logic:='0';
begin
process(clk)
begin
if (clk='1' and clk'event) then
clk_div <= clk_div+1;
end if;
end process;

int_clk <= clk_div(20);
process(int_clk,rst)
begin
if(rst='1') then q<='0'; qb<='1';
elsif (int_clk='1' and int_clk'event) then
if (s='0' and r='0') then q<=q; qb<=qb;
elsif (s='0' and r='1') then q<='0'; qb<='1';
elsif (s='1' and r='0') then q<='1'; qb<='0';
elsif (s='1' and r='1') then q<='Z'; qb<='Z';
end if;
end if;
end process;
end Behavioral;

16. JK flip flop
entity jk_flip_flop is
port(j,k,rst,clk: in std_logic;
q,qb: inout std_logic);
end jk_flip_flop;
architecture Behavioral of jk_flip_flop is
signal clk_div: std_logic_vector(25 downto 0):=(others=>'0');
signal int_clk: std_logic:='0';
begin
process(clk)
begin
if (clk='1' and clk'event) then
clk_div<=clk_div+1;
end if;
end process;
int_clk<=clk_div(20);
process(int_clk,rst)
begin
if (rst='1') then q<='0';
elsif (int_clk='1' and int_clk'event) then
if (j='0' and k='0') then q<=q;
elsif (j='0' and k='1') then q<='0';
elsif (j='1' and k='0') then q<='1';
elsif (j='1' and k='1') then q<=not q;
end if;
end if;
end process;
qb<=not q;
end Behavioral;

17. 4 bit counter with asynchronous reset
entity async_counter is
port(clk,rst: in std_logic;
count: inout std_logic_vector(3 downto 0));
end async_counter;
architecture Behavioral of async_counter is
signal clk_div: std_logic_vector(25 downto 0):=(others =>'0');
signal int_clk: std_logic:='0';
begin
process(clk)
begin
if (clk='1' and clk'event) then
clk_div <= clk_div + 1;
end if;
end process;
int_clk <= clk_div(20);
process(rst,int_clk)
begin
if (rst = '1') then count <= (others=>'0');
elsif (int_clk='1' and int_clk'event) then
count <= count+1;
end if;
end process;
end Behavioral;

18. 4 bit counter with synchronous reset
entity sync_counter is
port(clk,rst: in std_logic;
count: inout std_logic_vector(3 downto 0));
end sync_counter;
architecture Behavioral of sync_counter is
signal clk_div: std_logic_vector(25 downto 0):=(others =>'0');
signal int_clk: std_logic:='0';
begin
process(clk)
begin
if (clk='1' and clk'event) then
clk_div <= clk_div + 1;
end if;
end process;
int_clk <= clk_div(20);
process(int_clk,rst)
begin
if (int_clk='1' and int_clk'event) then
if (rst = '1') then
count <= (others=>'0');
else
count <= count+1;
end if;
end if;
end process;
end Behavioral;

19. 4 bit BCD up/down counter
VHDL
entity up_down_counter is
port(clk,rst,up_down: in std_logic;
Q: out std_logic_vector(3 downto 0));
end up_down_counter;
architecture Behavioral of up_down_counter is
signal clk_div: std_logic_vector(25 downto 0):=(others=>'0');
signal int_clk: std_logic:='0';
signal bcd: integer range 0 to 9;
begin
process(bcd)
begin
case bcd is
when 0 => Q <= "0000";
when 1 => Q <= "0001";
when 2 => Q <= "0010";
when 3 => Q <= "0011";
when 4 => Q <= "0100";
when 5 => Q <= "0101";
when 6 => Q <= "0110";
when 7 => Q <= "0111";
when 8 => Q <= "1000";
when 9 => Q <= "1001";
when others => Q <= "1111";
end case;
end process;
process(clk)
begin
if(clk'event and clk='1') then
clk_div<= clk_div+1;
end if;
end process;
int_clk<=clk_div(22);
process(int_clk,rst)
begin
if(rst='1') then bcd<=0;
else
if(int_clk'event and int_clk='1') then
if(up_down='1') then
if(bcd=9) then bcd<=0;
else bcd<=bcd+1;
end if;
end if;
if(up_down='0') then
if(bcd=0) then bcd<=9;
else bcd<=bcd-1;
end if;
end if;
end if;
end if;
end process;
end Behavioral;

20. Any sequence counter
VHDL
entity any_seq is
port(clk,rst: in std_logic;
count:out std_logic_vector(3 downto 0));
end any_seq;
architecture Behavioral of any_seq is
signal clk_div:std_logic_vector(25 downto 0):=(others=>'0');
signal int_clk:std_logic:='0';
signal r : integer :='0';
type arom is array(0 to 4) of std_logic_vector(3 downto 0);
signal drom:arom:=("1000","0011","0010","0100","0000");
begin
process(clk)
begin
if (clk='1' and clk'event) then
clk_div<= clk_div+1;
end if;
end process;
int_clk<=clk_div(20);
process(rst,int_clk)
begin
if (rst='1') then count<="0000";
elsif (int_clk'event and int_clk='1') then
r<=r+1;
count<=drom(r);
end if;
end process;
end behavioral;

VERILOG CODES FOR 4TH SEM ELECTRONIC AND COMMUNICATION STUDENTS (VTU)

2009-04-19T10:41:00.000-07:00

HERE U WILL FIND ALL THE VERILOG CODES NECESSARY FOR YOUR SYLLABUS

// EXPT NO 1.VERLOG CODE FOR ALL BASIC GATES
module basic_gates(a,b, op_and,op_or,op_nand,op_xor,op_nor,op_not,op_xnor);
input a,b;//Two inputs a and b
output op_and,op_or,op_nand,op_xor,op_nor,op_not,op_xnor;
assign op_and=a & b;
assign op_or=a | b;
assign op_nand=~(a & b);
assign op_nor=~(a | b);
assign op_not=~a;
assign op_xor=a ^ b;
assign op_xnor=~(a ^ b);
endmodule

// EXPT 2A. VERILOG CODE FOR THE IMPLEMENTATION OF HALF ADDER.
module half_adder(a,b, sum,cout);
input a,b;
output sum,cout;
sum=a ^ b;
cout=a & b;
endmodule

//EXPT 2B. VERILOG CODE FOR FULL ADDER USING STRUCYURAL MODULING.
// component ha(half adder).
module ha(a,b, s,c);
input a,b;
output s,c;
assign s=a^b;
assign c=a&b;
endmodule
// full adder using two half adders and or gate
module full_adder_structural(a,b,cin, sum,cout);
input a,b,cin;
output sum,cout;
wire c1,c2,s1;
ha u1(a,b,s1,c1);
ha u2(s1,cin,sum,c2);
or (cout,c1,c2);
endmodule

//EXPT 2C. VERILOG CODE FOR FULL ADDER (DATA FLOW MODEL).
module full_adder_data_flow(a,b,cin, sum,cout);
input a,b,cin;
output sum,cout;
assign sum=a ^ b ^ cin;
assign cout=( a & b ) | ( b & cin ) | ( cin & a );
endmodule
//EXPT NO 2D. VERILOG CODE FOR THE FULL-ADDER(BEHAVIORAL MODEL).
module full_adder_behavioral(a,b,cin,sum,cout);
input a,b,cin;
output reg sum,cout;// o/p are to be declared as registers
reg T1,T2,T3,S1;// as variables in VHDL
always@(a,b,cin)
begin
T1=a&b;
T2=b&cin;
T3=cin&a;
Cout=T1 | T2 | T3;
S1=a^b;
sum=S1^cin;
end
endmodule
// EXPT 2E. VERILOG CODE FOR FULL-ADDER (MIXED STYLE OF MODEL).
module full_adder_mixed(a,b,cin, sum,cout);
input a,b,cin;
output sum, cout;
reg cout;
wire s1;// as signal in vhdl
reg t1,t2,t3;// as variables in vhdl
xor u1(s1,a,b);// structural xor gate
assign sum=s1 ^ cin;// data flow
// carry using behavioral description
always@(a,b,cin)
begin
t1=a & b;
t2=a & cin;
t3=cin & b;
cout=t1 | t2 | t3;
end
endmodule

// EXPT 3. VERILOG CODE FOR 8:1 MUX
module MUX8TO1(sel, A,B,C,D,E,F,G,H, MUX_OUT);
input [2:0] sel;
input A,B,C,D,E,F,G,H;
input reg MUX_OUT;
always@(A,B,C,D,E,F,G,H,sel)
begin
case(sel)
3'd0:MUX_OUT=A;
3'd1:MUX_OUT=B;
3'd2:MUX_OUT=C;
3'd3:MUX_OUT=D;
3'd4:MUX_OUT=E;
3'd5:MUX_OUT=F;
3'd6:MUX_OUT=G;
3'd7:MUX_OUT=H;
default:; // indicates null
endcase
end
endmodule

/* EXPT 4. VERILOG CODE FOR 2 TO 4 DECODER( SYNCHRONOUS WITH ENABLE).*/
module decoder_2to4(i, en, y);
input [1:0] i;
input en;
output reg [3:0] y;
always@(i,en)
begin
if(en==1)
y=4'd0;
else
case(i)
2'd0:y=4'b0001;
2'd1:y=4'b0010;
2'd2:y=4'b0100;
default:y=4'b1000;
endcase
end
endmodule
// EXPT NO 5A. VERILOG CODE FOR 8 TO 3 ENCODER (WITHOUT PRIORITY).
module encoder_8to3_without_priority(i, en, y);
input [7:0] i;
input en;
output reg [2:0] y;
always@(i,en)
begin
if(en==1)
y=4'd0;
else
case(i)
8'b00000001:y=3'd0;
8'b00000010:y=3'd1;
8'b00000100:y=3'd2;
8'b00001000:y=3'd3;
8'b00010000:y=3'd4;
8'b00100000:y=3'd5;
8'b01000000:y=3'd6;
8'b10000000:y=3'd7;
default:;
endcase
end
endmodule
// EXPT 5B. VERILOG CODE FOR 8 TO 3 ENCODER (WITH PRIORITY).
module encoder_8to3_with_priority(i, en, y);
input [7:0] i;
input en;
output reg [2:0] y;
always@(i,en)
begin
if(en==1)
y=3'd0;
else
casex(i)
8'b1xxxxxxx:y=3'd7;
8'b01xxxxxx:y=3'd6;
8'b001xxxxx:y=3'd5;
8'b0001xxxx:y=3'd3;
8'b00001xxx:y=3'd4;
8'b000001xx:y=3'd2;
8'b0000001x:y=3'd1;
default:y=3'd0;
endcase
end
endmodule
// EXPT 6. VERILOG CODE FOR 4 BIT BINARY TO GRAY CONVERTER.
module binary_to_gray_4bit(b, g);
input [3:0] b;
output [3:0] g;
assign g[3]=b[3];
assign g[2]=b[3] ^ b[2];
assign g[1]=b[2] ^ b[1];
assign g[0]=b[1] ^ b[0];
endmodule
// 7a. VHDL CODE FOR 1:8 DEMULTIPLEXER.
module demux_1to8(i, sel, y);
input i;
input [2:0] sel;
output reg [7:0] y;
always@(i,sel)
begin
y=8'd0;
case(sel)
3'd0:y[0]=i;
3'd1:y[1]=i;
3'd2:y[2]=i;
3'd3:y[3]=i;
3'd4:y[4]=i;
3'd5:y[5]=i;
3'd6:y[6]=i;
default:y[7]=i;
endcase
end
endmodule

// 7B. COMBINATIONAL VERILOG CODE FOR N BIT COMPARATOR.
module comparator(a,b, alb,agb,aeb);
parameter N=3;
input [N:0] a,b;
output reg alb,agb,aeb;
always@(a,b)
begin
if(aelse alb=1'b0;
if(a>b) agb=1'b1;
else agb=1'b0;
if(a==b) aeb=1'b1;
else aeb=1'b0;
end
endmodule
// SEQUENTIAL CIRCUITS.
// EXPT NO 8. VERILOG CODE FOR FOLLOWING FLIP-FLOPS.
// 8A). SR FLIP-FLOP
module sr_flipflop(s,r,clk, q,qbar);
input s,r,clk;
output reg q,qbar;
reg [20:0] clk_div=21'd0;
reg int_clk;
wire [1:0] temp;
always@(clk
begin
clk_div=clk_div+1;
int_clk=clk_div[20];
end
always@(int_clk)
begin
temp={s,r};
case(temp)
2'b00:begin q=q; qbar=qbar; end
2'b01:begin q=1,b0; qbar=~q; end
2'b10:begin q=1'b1; qbar=~q; end
default:begin q=1'bz; qbar=1'bz; end
endcase
end
endmodule
// 8B). D FLIP-FLOP
module d_ff(d,clk, q,qb);
input d,clk;
output reg q,qb;
reg [22:0] clk_div=23'd0;
reg int_clk;
always@(posedge(clk))
begin
clk_div=clk_div+1;
int_clk=clk_div[21];
end
always@(posedge(int_clk))
begin
if(d==0)
q=1'b0;
else
q=1'b1;
qb=~q;
end
endmodule
// 8C).JK FLIP-FLOP.
module jk_ff(jk, clk, q,qb);
input [1:0] jk;
input clk;
output reg q,qb;
reg [22:0] clk_div=23'd0;
reg int_clk;
always@(posedge(clk))
begin
clk_div=clk_div+1;
int_clk=clk_div[21];
end
always@(posedge(int_clk))
begin
case(jk)
2'b01:q=1'b0;
2'b10:q=1'b1;
2'b11:q=~q;
default:q=q;
endcase
qb=~q;
end
endmodule
// 8d). T FLIP-FLOP.
module t_ff(t,clk, q,qb);
input t,clk;
output reg q,qb;
reg [22:0] clk_div=23'd0;
reg int_clk;
always@(posedge(clk))
begin
clk_div=clk_div+1;
int_clk=clk_div[21];
end
always@(posedge(int_clk))
begin
if(t==0)
q=1'b0;
else
q=~q;
qb=~q;
end
endmodule
// 9. VERILOG CODE FOR 8 BIT ALU.
module alu_8_bit(x,y, opcode, yout);
input [7:0] x,y;
input [2:0] opcode;
output reg [15:0] yout;
always@(x,y,opcode)
begin
case(opcode)
3'b000:yout=x+y;
3'b001:yout=x-y;
3'b010:yout=x*y;
3'b011:yout=x&y;
3'b100:yout=x|y;
3'b101:yout=~x;
3'b110:yout=x^y;
default:yout=~(x&y);
endcase
end
endmodule
// EXPT NO 10 A.DESIGN 4 BIT BINARY COUNTER (SYNCHRONOUS RESET).
module binary_count_sync(clk,rst, count);
input clk,rst;
output reg [3:0] count;
reg [21:0] clk_div=22'd0;
reg int_clk;
always@(posedge(clk))
begin
clk_div=clk_div+1;
int_clk<=clk_div[20];
end
always@(posedge(int_clk))
begin
if(rst==1)
count=3'd0;
else
count=count+1;
end
endmodule
// EXPT NO 10 B.BINARY COUNTER WITH ASYNCHRONOUS RESET.
module binary_count_ashyn(clk,rst, count);
input clk,rst;
output reg [3:0] count;
reg [21:0] clk_div=22'd0;
reg int_clk;
always@(posedge(clk) )
begin
clk_div=clk_div+1;
int_clk=clk_div[20];
end
always@(posedge(int_clk),posedge(rst))
begin
if(rst==1)
count=4'd0;
else if(int_clk==1)
count=count+1;
end
endmodule

// EXPT NO 10 C. VRILOG CODE FOR ANY SEQUENCE COUNTER
module any_sequence_counter(clk, q);
input clk;
output reg [3:0] q;
reg [21:0] clk_div=22'd0;
reg int_clk;
reg temp;
always@(posedge(clk))
begin
clk_div=clk_div+1;
int_clk=clk_div[20];
end
always@(posedge(int_clk))
begin
case(temp)
4'b0000:temp=4'b0010;
4'b0010:temp=4'b0100;
4'b0100:temp=4'b1000;
4'b1000:temp=4'b1100;
4'b1100:temp=4'b1110;
default:temp=4'b0000;// first sequence is 0000
endcase
q=temp;
end
endmodule
// EXPT 11. BINARY UP DOWN COUNTER
module binary_up_down_counter(clk,up_down, q);
input clk,up_down;
output reg [3:0] q;
reg [21:0] clk_div=22'd0;
reg int_clk;
integer temp=0;
always@(posedge(clk))
begin
clk_div=clk_div+1;
int_clk=clk_div[20];
end
always@(int_clk)
begin
if(up_down==1)
if(temp==9)
temp=0;
else
temp=temp+1;
else
if(temp==0)
temp=9;
else
temp=temp-1;
end
always@(temp)
begin
case(temp)
0:q=4'd0;
1:q=4'd1;
2:q=4'd2;
3:q=4'd3;
4:q=4'd4;
5:q=4'd5;
6:q=4'd6;
7:q=4'd7;
8:q=4'd8;
9:q=4'd9;
default:;
endcase
end
endmodule